1. Field of the Invention
The present invention relates to a system bus controller and related method, and more specifically, to a system bus controller and related method for efficiently managing the bus transaction in a computer system.
2. Description of the Prior Art
Generally, a bus is a channel for transmitting entry commands and data in a computer system and providing bus transactions between devices in the computer system. Referring to FIG. 1, a prior art computer system 10 comprises a bus 12, as first bus master 14, a second bus master 16, a first bus slave 18, and a second slave 20. The first bus master 14, the second bus master 16, the first bus slave 18, and the second bus slave 20 are electrically connected to the bus 12. The above-mentioned first bus master 14 and the second bus master 16 are connected to a central processing unit (CPU) or a microprocessor control unit (MCU) that transmits and receives entry commands and execute received entry commands. The first bus slave 18 and the second bus slave 20 are connected to an I/O device to receive entry commands and execute received entry commands.
When the first bus master 14 (or second bus master 16) receives control of the bus 12 and then transmits entry commands to the first slave 18 (or second slave 20) through the bus 12, the first bus master 14 waits and occupies the bus 12 until the entry commands are executed by the first bus slave 14 and an acknowledge signal and a response signal are transmitted to the first bus master 14 through the bus 12. That the first bus master 14 occupies the bus 12 is dependent on the type of the bus 12. In addition, the first bus master 14 reinstates a stand-by mode to execute a next entry command. This means that in the period that the first bus master 14 is waiting for the acknowledge signal and the response signal transmitted by the first bus slave, the first bus master 14 is not capable of transmitting any entry commands to the first bus slave 18 through the bus 12, or the first bus master 14 and the second bus master 16 are not capable of transmitting any entry commands to the first bus slave 18 and the second bus slave 20 through the bus 12. When the speed that an entry command is executed by the first bus slave is quite slow, the efficiency of the computer system 10 is also reduced. This disadvantage is significant when the computer system is performing processing that requires high speed.